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lt3580 1 3580fg typical application features applications description boost/inverting dc/dc converter with 2a switch, soft-start, and synchronization the lt ? 3580 is a pwm dc/dc converter containing an internal 2a, 42v switch. the lt3580 can be configured as either a boost, sepic or inverting converter. capable of generating 12v at 550ma or C12v at 350ma from a 5v input, the lt3580 is ideal for many local power supply designs. the lt3580 has an adjustable oscillator, set by a resistor from the rt pin to ground. additionally, the lt3580 can be synchronized to an external clock. the free running or synchronized switching frequency range of the part can be set between 200khz and 2.5mhz. the lt3580 also features innovative shdn pin circuitry that allows for slowly varying input signals and an adjust- able undervoltage lockout function. additional features such as frequency foldback and soft-start are integrated. the lt3580 is available in tiny 3mm 3mm 8-lead dfn and 8-lead msop packages. 1.2mhz, 5v to 12v boost converter achieves over 88% efficiency n 2a internal power switch n adjustable switching frequency n single feedback resistor sets v out n synchronizable to external clock n high gain shdn pin accepts slowly varying input signals n wide input voltage range: 2.5v to 32v n low v cesat switch: 300mv at 1.5a (typical) n integrated soft-start function n easily configurable as a boost or inverting converter n user configurable undervoltage lockout (uvlo) n tiny 8-lead 3mm 3mm dfn and 8-lead msop packages n vfd bias supplies n tft-lcd bias supplies n gps receivers n dsl modems n local power supply efficiency and power loss l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 10f v out 12v 550ma 4.2h 130k v in 5v v in sw 3580 ta01 lt3580 75k 10k shdn gnd fb vc sync ss rt 1nf 0.1f 2.2f load current (ma) 0 50 efficiency (%) power loss (mw) 55 65 70 75 400 95 3580 ta01b 60 200 100 500 300 600 80 85 90 0 200 600 1200 400 800 1000
lt3580 2 3580fg absolute maximum ratings v in voltage ................................................. ? 0.3v to 32v sw voltage ................................................ ? 0.4v to 42v rt voltage ................................................... ? 0.3v to 5v ss and fb voltage .................................... ? 0.3v to 2.5v vc voltage ................................................... ? 0.3v to 2v shdn voltage ............................................ ? 0.3v to 32v sync voltage ............................................ ? 0.3v to 5.5v (note 1) top view dd package 8-lead ( 3mm s 3mm ) plastic dfn 5 6 7 8 9 gnd 4 3 2 1fb vc v in sw sync ss rt shdn t jmax = 125c, ja = 43c/w exposed pad (pin 9) is gnd, must be soldered to pcb 1 2 3 4 fb vc v in sw 8 7 6 5 sync ss rt shdn top view 9 gnd ms8e package 8-lead plastic msop ja = 35c/w to 40c/w exposed pad (pin 9) is gnd, must be soldered to pcb pin configuration order information lead free finish tape and reel part marking* package description temperature range lt3580edd#pbf lt3580edd#trpbf lcxy 8-lead (3mm 3mm) plastic dfn ? 40c to 125c lt3580idd#pbf lt3580idd#trpbf lcxy 8-lead (3mm 3mm) plastic dfn ? 40c to 125c lt3580ems8e#pbf lt3580ems8e#trpbf ltdcj 8-lead plastic msop ? 40c to 125c lt3580ims8e#pbf lt3580ims8e#trpbf ltdcj 8-lead plastic msop ? 40c to 125c lt3580hms8e#pbf lt3580hms8e#trpbf ltdcj 8-lead plastic msop ? 40c to 150c lt3580mpms8e#pbf lt3580mpms8e#trpbf ltdcj 8-lead plastic msop ? 55c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a l abel on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating junction temperature range lt3580e (notes 2, 5) ......................... ? 40c to 125c lt3580i (notes 2, 5) .......................... ? 40c to 125c lt3580h (notes 2, 5) ........................? 40c to 150c lt3580mp (notes 2, 5) ..................... ? 55c to 125c storage temperature range ..................? 65c to 150c
lt3580 3 3580fg note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3580e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3580i is guaranteed over the full C40c to 125c operating junction temperature range. the lt3580h is guaranteed over the full C40c to electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 5v, v shdn = v in unless otherwise noted. (note 2) parameter conditions min typ max units operating voltage range l 2.5 32 v positive feedback voltage l 1.195 1.215 1.230 v negative feedback voltage l 0 5 12 mv positive fb pin bias current v fb = positive feedback voltage, current into pin l 81 83.3 85 a negative fb pin bias current v fb = negative feedback voltage, current out of pin (lt3580e, lt3580i, lt3580mp) (lt3580h) l l 81 81 83.3 83.3 85.5 86 a a error amplifier transconductance 230 mhos error amplifier voltage gain 70 v/v quiescent current v shdn = 2.5v, not switching 1 1.5 ma quiescent current in shutdown v shdn = 0v 0 1 a reference line regulation 2.5v v in 32v 0.01 0.05 %/v switching frequency, f osc r t = 45.3k (lt3580e, lt3580i, lt3580h) r t = 45.3k (lt3580mp) r t = 464k (lt3580e, lt3580i, lt3580h) r t = 464k (lt3580mp) l l l l 1.8 1.8 180 180 2 2 200 200 2.2 2.25 220 225 mhz mhz khz khz switching frequency in foldback compared to normal f osc 1/4 ratio switching frequency set range syncing or free running l 200 2500 khz sync high level for synchronization l 1.3 v sync low level for synchronization l 0.4 v sync clock pulse duty cycle v sync = 0v to 2v 35 65 % recommended minimum sync ratio f sync /f osc 3/4 minimum off-time 60 ns minimum on-time 100 ns switch current limit m inimum duty cycle (note3) (lt3580e, lt3580i, lt3580h) minimum duty cycle (note3) (lt3580mp) maximum duty cycle (notes 3, 4) (lt3580e, lt3580i, lt3580mp) maximum duty cycle (notes 3, 4) (lt3580h) l l l l 2.2 2.15 1.6 1.55 2.5 2.2 1.9 1.9 2.8 2.8 2.6 2.6 a a a a switch v cesat i sw = 1.5a 300 mv switch leakage current v sw = 5v 0.01 1 a soft-start charging current v ss = 0.5v l 468 a shdn minimum input voltage high active mode, shdn rising (lt3580e, lt3580i) active mode, shdn rising (lt3580h, lt3580mp) active mode, shdn falling (lt3580e, lt3580i) active mode, shdn falling (lt3580h, lt3580mp) l l l l 1.27 1.25 1.24 1.22 1.32 1.32 1.29 1.29 1.38 1.4 1.33 1.35 v v v v shdn input voltage low shutdown mode l 0.3 v shdn pin bias current v shdn = 3v v shdn = 1.3v v shdn = 0v 9.7 40 11.6 0 60 13.4 0.1 a a a 150c operating junction temperature range. the lt3580mp is guaranteed over the full C55c to 125c operating junction temperature range. operating lifetime is derated at junction temperatures greater than 125c. note 3: current limit guaranteed by design and/or correlation to static test. note 4: current limit measured at equivalent switching frequency of 2.5mhz. note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability.
lt3580 4 3580fg typical performance characteristics switch current limit at 1mhz switch saturation voltage switch current limit at minimum duty cycle switch current limit at minimum duty cycle positive feedback voltage switching waveforms for figure 14 circuit oscillator frequency oscillator frequency during soft-start internal uvlo t a = 25c unless otherwise specified duty cycle (%) 10 0 switch current limit (a) 0.5 1.0 1.5 2.0 30 50 70 90 3580 g01 2.5 20 40 60 80 switch current (a) 0 saturation voltage (mv) 200 250 300 2 3580 g02 150 100 0 0.5 1 1.5 50 400 350 ss voltage (mv) 0 0 switch current (a) 0.5 1.0 1.5 2.0 200 400 600 800 3580 g03 1000 1200 2.5 temperature (c) C50 0 switch current limit (a) 0.5 1.0 1.5 2.0 2.5 3.0 0 50 100 3580 g04 temperature (c) C50 C25 1.19 fb voltage (v) 1.21 1.24 0 50 75 3580 g05 1.20 1.23 1.22 25 100 125 v out 50mv/div ac coupled v sw 10v/div i l 0.5a/div 200ns/div 3580 g06 temperature (c) C50 frequency (mhz) 1.9 2.1 2.3 3580 g07 1.7 1.5 1.1 0 50 100 1.3 2.7 r t = 35.7k 2.5 r t = 75k fb voltage (v) 0 0 normalized oscillator frequency (f/f nom ) 1/4 1/2 t a = C35c t a = 25c t a = 100c 1/3 1 0.2 0.4 inverting configurations boosting configurations 0.6 0.8 3580 g08 1.0 1.2 temperature (c) C50 2.20 v in voltage (v) 2.22 2.26 2.28 2.30 2.40 2.34 0 50 3580 g09 2.24 2.36 2.38 2.32 100
lt3580 5 3580fg typical performance characteristics shdn pin current shdn pin current active/lockout threshold t a = 25c unless otherwise specified pin functions fb (pin 1): positive and negative feedback pin. for a boost or inverting converter, tie a resistor from the fb pin to v out according to the following equations: r fb = v out ? 1.215 () 83.3 ? 10 ? 6 ; boost or sepic converter r fb = v out + 5mv () 83.3 ? 10 ? 6 ; inverting converter vc (pin 2): error amplifier output pin. tie external compensation network to this pin. v in (pin 3): input supply pin. must be locally bypassed. sw (pin 4): switch pin. this is the collector of the internal npn power switch. minimize the metal trace area connec- ted to this pin to minimize emi. shdn (pin 5): shutdown pin. in conjunction with the uvlo (undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. drive below 1.24v (lt3580e, lt3580i) or 1.22v (lt3580h, lt3580mp) to disable the chip. drive above 1.38v (lt3580e, lt3580i) or 1.40v (lt3580h, lt3580mp) to activate chip and restart the soft-start sequence. do not float this pin. rt (pin 6): timing resistor pin. adjusts the switching frequency. place a resistor from this pin to ground to set the frequency to a fixed free running level. do not float this pin. ss (pin 7): soft-start pin. place a soft-start capacitor here. upon start-up, the ss pin will be charged by a (nominally) 275k resistor to about 2.2v. sync (pin 8): to synchronize the switching frequency to an outside clock, simply drive this pin with a clock. the high voltage level of the clock needs to exceed 1.3v, and the low level should be less 0.4v. drive this pin to less than 0.4v to revert to the internal free running clock. see the applications information section for more information. gnd (exposed pad pin 9): ground. exposed pad must be soldered directly to local ground plane. shdn voltage (v) 0 0 shdn pin current (a) 5 10 15 20 25 30 0.5 1 C50c 1.5 2 3580 g10 100c 20c shdn voltage (v) 0 shdn pin current (a) 200 250 C50c 20c 100c 300 15 25 3580 g11 150 100 510 20 30 50 0 temperature (c) C50 1.20 shdn voltage (v) 1.22 1.26 1.28 1.30 1.40 1.34 0 50 3580 g12 1.24 1.36 1.38 1.32 100 shdn rising shdn falling
lt3580 6 3580fg block diagram the lt3580 uses a constant-frequency, current mode con- trol scheme to provide excellent line and load regulation. refer to the block diagram which shows the lt3580 in a boost configuration. at the start of each oscillator cycle, the sr latch (sr1) is set, which turns on the power switch, q1. the switch current flows through the internal current sense resistor generating a voltage proportional to the switch current. this voltage (amplified by a4) is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the pwm comparator a3. when this voltage exceeds the level at the negative input of a3, the sr latch is reset, turning off the power switch. the level at the negative input of a3 (vc pin) is set by the error amplifier a1 (or a2) and is simply an amplified version of the difference between the feedback voltage (fb pin) and the reference voltage (1.215v or 5mv depending on the configuration). in this manner, the error amplifier sets the correct peak current level to keep the output in regulation. the lt3580 has a novel fb pin architecture that can be used for either boost or inverting configurations. when configured as a boost converter, the fb pin is pulled up to the internal bias voltage of 1.215v by the r fb resistor connected from v out to fb. comparator a2 becomes inactive and comparator a1 performs the inverting amplification from fb to vc. when the lt3580 is in an inverting configuration, the fb pin is pulled down to 5mv by the r fb resistor connected from v out to fb. comparator a1 becomes inactive and comparator a2 performs the noninverting amplification from fb to vc. C + C + C + C + + C 7 5 3 1.215v reference adjustable oscillator frequency foldback ramp generator comparator discharge detect ss vc 275k q2 sr2 r s 14.6k 14.6k q sr1 a3 a4 a1 a2 sync n rt shdn fb 1.3v vc c1 sw 0.01 gnd r t r fb driver l1 d1 i limit v in v ou t c ss c c c in r c v in soft- start sync block uvlo r s q 6 2 1 3580 bd 8 4 q1 9 operation
lt3580 7 3580fg operation figure 1. sepic topology allows for the input to span the output voltage. coupled or uncoupled inductors can be used. follow noted phasing if coupled figure 2. dual inductor inverting topology results in low output ripple. coupled or uncoupled inductors can be used. follow noted phasing if coupled d1 shutdown l2 c3 l1 r1 v in > v out or v in = v out or v in < v out v out v in sw 3580 f01 lt3580 rt rc c2 shdn gnd fb vc sync ss rt cc c ss c1 + + ? ? d1 shutdown c3 l1 r1 v in v out v in sw 3580 f02 lt3580 rt rc c2 shdn gnd fb vc sync ss rt cc c ss c1 l2 + + ?? sepic topology the lt3580 can be configured as a sepic (single-ended primary inductance converter). this topology allows for the input to be higher, equal, or lower then the desired output voltage. output disconnect is inherently built into the sepic topology, meaning no dc path exists between the input and output. this is useful for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. inverting topology the lt3580 can also work in a dual inductor inverting topology. the parts unique feedback pin allows for the inverting topology to be built by simply changing the connection of external components. this solution results in very low output voltage ripple due to inductor l2 in series with the output. abrupt changes in output capacitor current are eliminated because the output inductor deliv- ers current to the output during both the off-time and the on-time of the lt3580 switch. start-up operation several functions are provided to enable a very clean start-up for the lt3580. ? first, the shdn pin voltage is monitored by an internal voltage reference to give a precise turn-on voltage level. an external resistor (or resistor divider) can be connected from the input power supply to the shdn pin to provide a user-programmable undervoltage lockout function. ? second, the soft-start circuitry provides for a gradual ramp-up of the switch current. when the part is brought out of shutdown, the external ss capacitor is first discharged (providing protection against shdn pin glitches and slow ramping), then an integrated 275k resistor pulls the ss pin up to ~2.2v. by connecting an external capacitor to the ss pin, the voltage ramp rate on the pin can be set. typical values for the soft-start capacitor range from 100nf to 1f. ? finally, the frequency foldback circuit reduces the switching frequency when the fb pin is in a nominal range of 350mv to 900mv. this feature reduces the minimum duty cycle that the part can achieve thus allowing better control of the switch current during start-up. when the fb voltage is pulled outside of this range, the switching frequency returns to normal. current limit and thermal shutdown operation the lt3580 has a current limit circuit not shown in the block diagram. the switch current is consistently moni- tored and not allowed to exceed the maximum switch current at a given duty cycle (see the electrical charac- teristics table). if the switch current reaches this value, the sr latch (sr1) is reset regardless of the state of the comparator (a1/a2). also not shown in the block diagram is the thermal shutdown circuit. if the temperature of the part exceeds approximately 165c, the sr2 latch is set regardless of the state of the comparator (a1/a2). a full soft-start cycle will then be initiated. the current limit and thermal shutdown circuits protect the power switch as well as the external components connected to the lt3580.
lt3580 8 3580fg setting output voltage the output voltage is set by connecting a resistor (r fb ) from v out to the fb pin. r fb is determined from the following equation: r fb = |v out ? v fb | 83.3a where v fb is 1.215v (typical) for non-inverting topologies (i.e., boost and sepic regulators) and 5mv (typical) for inverting topologies (see the electrical characteristics). power switch duty cycle in order to maintain loop stability and deliver adequate current to the load, the power npn (q1 in the block dia- gram) cannot remain on for 100% of each clock cycle. the maximum allowable duty cycle is given by: dc max = (t p ? min off time) t p ? 100% where t p is the clock period and min off time (found in the electrical characteristics) is typically 60ns. the application should be designed so that the operating duty cycle does not exceed dc max . duty cycle equations for several common topologies are given below, where v d is the diode forward voltage drop and v cesat is typically 300mv at 1.5a. for the boost topology: dc ? v out ? v in + v d v out + v d ? v cesat for the sepic or dual inductor inverting topology (see figures 1 and 2): dc ? v d + |v out | v in + |v out | + v d ? v cesat the lt3580 can be used in configurations where the duty cycle is higher than dc max , but it must be operated in the discontinuous conduction mode so that the effective duty cycle is reduced. applications information inductor selection general guidelines : the high frequency operation of the lt3580 allows for the use of small surface mount inductors. for high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. to improve efficiency, choose inductors with more volume for a given inductance. the inductor should have low dcr (copper wire resistance) to reduce i 2 r losses, and must be able to handle the peak inductor current without saturating. note that in some applications, the current handling requirements of the inductor can be lower, such as in the sepic topology, where each inductor only carries a fraction of the total switch current. molded chokes or chip inductors usually do not have enough core area to sup- port peak inductor currents in the 2a to 3a range. to minimize radiated noise, use a toroidal or shielded inductor. note that the inductance of shielded types will drop more as current increases, and will saturate more easily. see table 1 for a list of inductor manufacturers. thorough lab evaluation is recommended to verify that the following guidelines properly suit the final application. table 1.inductor manufacturers coilcraft do3316p , mss7341 and lps4018 series www.coilcraft.com coiltronics dr, ld and cd series www.coiltronics.com murata lqh55d and lqh66s series www.murata.com sumida cdrh5d18b/hp , cdr6d23mn, cdrh6d26/hp , cdrh6d28, cdr7d28mn and cdrh105r series www.sumida.com tdk rlf7030 and vlcf4020 series www.tdk.com wrth we-pd and we-pd2 series www.we-online.com minimum inductance : although there can be a tradeoff with efficiency, it is often desirable to minimize board space by choosing smaller inductors. when choosing an inductor, there are two conditions that limit the minimum inductance; (1) providing adequate load current, and (2) avoidance of subharmonic oscillation. choose an inductance that is high enough to meet both of these requirements. adequate load current : small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be
lt3580 9 3580fg applications information provided to a load (i out ). in order to provide adequate load current, l should be at least: l > dc ? v in 2(f) i lim ? |v out |? i out v in ? ? ? ? ? ? ? for boost, topologies, or: l > dc ? v in 2( f) i lim ? v out ?i out v in ? ? i out ? ? ? ? ? ? ? ? for the sepic and inverting topologies. where: l = l1||l2 for uncoupled dual inductor topologies dc = switch duty cycle (see previous section) i lim = switch current limit, typically about 2.4a at 50% duty cycle (see the typical performance characteristics section). = power conversion efficiency (typically 88% for boost and 75% for dual inductor topologies at high currents). f = switching frequency negative values of l indicate that the output load current i out exceeds the switch current limit capability of the lt3580. avoiding subharmonic oscillations : the lt3580s internal slope compensation circuit will prevent subharmonic oscil- lations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a minimum value. in applications that operate with duty cycles greater than 50%, the inductance must be at least: l > v in ?2?dc?1 () (1 ? dc) ? (f) for boost, coupled inductor sepic, and coupled inductor inverting topologies, or: l1 l2 > v in ?2?dc?1 () (1 ? dc) ? (f) for the uncoupled inductor sepic and uncoupled inductor inverting topologies. maximum inductance : excessive inductance can reduce current ripple to levels that are difficult for the current com- parator (a3 in the block diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. the maximum inductance can be calculated by: l max = v in ?v cesat i min ? ripple ? dc f where l max is l1||l2 for uncoupled dual inductor topolo- gies and i min-ripple is typically 95ma. current rating : finally, the inductor(s) must have a rating greater than its peak operating current to prevent inductor saturation resulting in efficiency loss. in steady state, the peak input inductor current (continuous conduction mode only) is given by: i l1 ? peak = v out ?i out v in ? + v in ?dc 2?l1?f for the boost, uncoupled inductor sepic and uncoupled inductor inverting topologies. for uncoupled dual inductor topologies, the peak output inductor current is given by: i l2 ? peak = i out + v out ?1?dc () 2?l2?f for the coupled inductor topologies: i out 1 + v out ? v in ? ? ? ? ? ? + v in ?dc 2?l?f note: inductor current can be higher during load transients. it can also be higher during start-up if inadequate soft-start capacitance is used. capacitor selection low esr (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. multilayer ceramic capacitors are an excellent choice, as they have an extremely low esr and are available in very small packages. x5r or x7r dielectrics are preferred, as
lt3580 10 3580fg applications information these materials retain their capacitance over wider voltage and temperature ranges. a 4.7f to 20f output capaci- tor is sufficient for most applications, but systems with very low output currents may need only a 1f or 2.2f output capacitor. always use a capacitor with a sufficient voltage rating. many capacitors rated at 2.2f to 20f, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired output voltage. solid tantalum or os-con capacitors can be used, but they will occupy more board area than a ceramic and will have a higher esr with greater output ripple. ceramic capacitors also make a good choice for the input decoupling capacitor, which should be placed as closely as possible to the lt3580. a 2.2f to 4.7f input capacitor is sufficient for most applications. table 2 shows a list of several ceramic capacitor manufac- turers. consult the manufacturers for detailed information on their entire selection of ceramic parts. table 2. ceramic capacitor manufacturers kemet www.kemet.com murata www.murata.com taiyo yuden www.t-yuden.com compensationadjustment to compensate the feedback loop of the lt3580, a series resistor-capacitor network in parallel with a single capacitor should be connected from the vc pin to gnd. for most applications, the series capacitor should be in the range of 470pf to 2.2nf with 1nf being a good starting value. the parallel capacitor should range in value from 10pf to 100pf with 47pf a good starting value. the compensation resistor, r c , is usually in the range of 5k to 50k. a good technique to compensate a new application is to use a 100k potentiometer in place of series resistor r c . with the series capacitor and parallel capacitor at 1nf and 47pf respectively, adjust the potentiometer while observing the transient response and the optimum value for r c can be found. figures 3a to 3c illustrate this process for the circuit of figure 14 with a load current stepped between 400ma and 500ma. figure 3a shows the transient response with r c equal to 1k. the phase margin is poor, as evidenced by the excessive ringing in the output voltage and inductor current. in figure 3b, the value of r c is increased to 3k, which results in a more damped response. figure 3c shows the results when r c is increased further to 10k. the transient response is nicely damped and the compensation procedure is complete. figure 3a. transient response shows excessive ringing figure 3b. transient response is better figure 3c. transient response is well damped v out 200mv/div ac coupled i l 0.5a/div 200s/div r c = 1k 3580 f03a v out 200mv/div ac coupled i l 0.5a/div 200s/div r c = 3k 3580 f03b v out 200mv/div ac coupled i l 0.5a/div 200s/div r c = 10k 3580 f03c
lt3580 11 3580fg applications information compensationtheory like all other current mode switching regulators, the lt3580 needs to be compensated for stable and efficient operation. two feedback loops are used in the lt3580 a fast current loop which does not require compensation, and a slower voltage loop which does. standard bode plot analysis can be used to understand and adjust the voltage feedback loop. as with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. figure 4 shows the key equivalent elements of a boost converter. because of the fast current control loop, the power stage of the ic, inductor and diode have been replaced by a combination of the equivalent transconductance amplifier g mp and the current controlled current source (which converts i vin to v in /v out ? i vin ). g mp acts as a current source where the peak input current, i vin , is proportional to the vc voltage. is the efficiency of the switching regulator, and is typically about 88%. note that the maximum output currents of g mp and g ma are finite. the limits for g mp are in the electrical characteristics section (switch current limit), and g ma is nominally limited to about 12a. from figure 4, the dc gain, poles and zeros can be cal- culated as follows: output pole: p1 = 2 2? ?r l ?c out error amp pole: p2 = 1 2? ?r o + r c ? ? ? ? ?c c error amp zero : z1 = 1 2? ?r c ?c c dc gain: (breaking loop at fb pin) a dc = a ol (0) = ? v c ? v fb ? ? i vin ? v c ? ? v out ? i vin ? ? v fb ? v out = g ma ?r 0 ( ) ?g mp ? ? v in v out ? r l 2 ? ? ? ? ? ? ? 0.5r2 r1 + 0.5r2 esr zero: z2 = 1 2? ?r esr ?c out rhp zero: z3 = v in 2 ?r l 2? ?v out 2 ?l high frequency pole: p3 > f s 3 phase lead zero: z4 = 1 2? ?r1?c pl phase lead pole: p4 = 1 2? ? r1? r2 2 r1 + r2 2 ?c pl error amp filter pole: p5 = 1 2? ? r c ?r o r c +r o ?c f ,c f < c c 10 the current mode zero (z3) is a right-half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. figure 4. boost converter equivalent model C + C + g ma r c r o r2 r2 c c : compensation capacitor c out : output capacitor c pl : phase lead capacitor c f : high frequency filter capacitor g ma : transconductance amplifier inside ic g mp : power stage transconductance amplifier r c : compensation resistor r l : output resistance defined as v out divided by i load(max) r o : output resistance of g ma r1, r2: feedback resistor divider network r esr : output capacitor esr 3580 f04 r1 fb c out c pl r l r esr v out i vin v c c c c f g mp 1.215v reference h ?v in v out ?i vin
lt3580 12 3580fg applications information using the circuit in figure 14 as an example, table 3 shows the parameters used to generate the bode plot shown in figure 5. table 3. bode plot parameters parameter value units comment r l 21.8 application specific c out 10 f application specific r esr 10 m application specific r o 305 k not adjustable c c 1000 pf adjustable c f 0 pf optional/adjustable c pl 0 pf optional/adjustable r c 10 k adjustable r1 130 k adjustable r2 14.6 k not adjustable v out 12 v application specific v in 5 v application specific g ma 230 mho not adjustable g mp 7 mho not adjustable l 4.2 h application specific f s 1.2 mhz adjustable in figure 5, the phase is C140 when the gain reaches 0db giving a phase margin of 40. the crossover frequency is 10khz, which is more than three times lower than the frequency of the rhp zero to achieve adequate phase margin. diode selection schottky diodes, with their low forward voltage drops and fast switching speeds, are recommended for use with the lt3580. the microsemi ups120 is a very good choice. where the input-to-output voltage differential exceeds 20v, use the ups140 (a 40v diode). these diodes are rated to handle an average forward current of 1a. oscillator the operating frequency of the lt3580 can be set by the internal free-running oscillator. when the sync pin is driven low (< 0.4v), the frequency of operation is set by a resistor from r t to ground. an internally trimmed timing capacitor resides inside the ic. the oscillator frequency is calculated using the following formula: f osc = 91.9 (r t + 1) where f osc is in mhz and r t is in k . conversely, r t (in k ) can be calculated from the desired frequency (in mhz) using: r t = 91.9 f osc ? 1 clock synchronization the operating frequency of the lt3580 can be synchronized to an external clock source. to synchronize to the external source, simply provide a digital clock signal into the sync pin. the lt3580 will operate at the sync clock frequency. the lt3580 will revert to the internal free-running oscillator clock after sync is driven low for a few free-running clock periods. driving sync high for an extended period of time effectively stops the operating clock and prevents latch sr1 from becoming set (see the block diagram). as a result, the switching operation of the lt3580 will stop. the duty cycle of the sync signal must be between 35% and 65% for proper operation. also, the frequency of the sync signal must meet the following two criteria: figure 5. bode plot for example boost converter frequency (hz) 10 60 gain (db) phase (deg) 80 100 120 140 100 1k 10k 100k 1m 3580 f05 40 20 0 C20 160 180 C120 C100 C80 C60 C40 C140 C160 C180 C200 C20 0 40 o at 10khz phase gain
lt3580 13 3580fg applications information (1) sync may not toggle outside the frequency range of 200khz to 2.5mhz unless it is stopped low to enable the free-running oscillator. (2) the sync frequency can always be higher than the free-running oscillator frequency, f osc , but should not be less than 25% below f osc . operating frequency selection there are several considerations in selecting the operating frequency of the converter. the first is staying clear of sensitive frequency bands, which cannot tolerate any spectral noise. for example, in products incorporating rf communications, the 455khz if frequency is sensitive to any noise, therefore switching above 600khz is desired. some communications have sensitivity to 1.1mhz, and in that case, a 1.5mhz switching converter frequency may be employed. the second consideration is the physical size of the converter. as the operating frequency goes up, the inductor and filter capacitors go down in value and size. the tradeoff is efficiency, since the switching losses due to npn base charge (see thermal calculations), schottky diode charge, and other capacitive loss terms increase proportionally with frequency. soft-start the lt3580 contains a soft-start circuit to limit peak switch currents during start-up. high start-up current is inherent in switching regulators in general since the feedback loop is saturated due to v out being far from its final value. the regulator tries to charge the output capacitor as quickly as possible, which results in large peak currents. the start-up current can be limited by connecting an external capacitor (typically 100nf to 1f) to the ss pin. this capacitor is slowly charged to ~2.2v by an internal 275k resistor once the part is activated. ss pin voltages below ~1.1v reduce the internal current limit. thus, the gradual ramping of the ss voltage also gradually increases the current limit as the capacitor charges. this, in turn, allows the output capacitor to charge gradually toward its final value while limiting the start-up current. in the event of a commanded shutdown or lockout ( shdn pin), internal undervoltage lockout (uvlo) or a thermal lockout, the soft-start capacitor is automatically discharged to ~200mv before charging resumes, thus assuring that the soft-start occurs after every reactivation of the chip. shutdown the shdn pin is used to enable or disable the chip. for most applications, shdn can be driven by a digital logic source. voltages above 1.38v enable normal active operation. voltages below 300mv will shutdown the chip, resulting in extremely low quiescent current. while the shdn voltage transitions through the lockout voltage range (0.3v to 1.24v) the power switch is disabled and the sr2 latch is set (see the block diagram). this causes the soft-start capacitor to begin discharging, which continues until the capacitor is discharged and active operation is enabled. although the power switch is disabled, shdn voltages in the lockout range do not necessarily reduce quiescent current until the shdn voltage is near or below the shutdown threshold. also note that shdn can be driven above v in or v out as long as the shdn voltage is limited to less than 32v. figure 6. chip states vs shdn voltage configurable undervoltage lockout figure 7 shows how to configure an undervoltage lockout (uvlo) for the lt3580. typically, uvlo is used in situations where the input supply is current-limited, has a relatively high source resistance, or ramps up/down slowly. a switching regulator draws constant power from the source, so source current increases as source voltage drops. this looks like a negative resistance load to the source and can cause the source to current-limit or latch low under low (hysteresis and tolerance) shutdown (low quiescent current) active (normal operation) lockout (power switch off, ss capacitor discharged) 1.24v 0.0v 1.38v 0.3v 3580 f06 shdn (v)
lt3580 14 3580fg applications information source voltage conditions. uvlo prevents the regulator from operating at source voltages where these problems might occur. the shutdown pin comparator has voltage hysteresis with typical thresholds of 1.32v (rising) and 1.29v (falling). resistor r uvlo2 is optional. r uvlo2 can be included to reduce the overall uvlo voltage variation caused by variations in shdn pin current (see the electrical character- istics). a good choice for r uvlo2 is 10k 1%. after choosing a value for r uvlo2 , r uvlo1 can be determined from either of the following: r uvlo1 = v in + ? 1.32v 1.32v r uvlo2 ? ? ? ? ? ? + 11.6 a or r uvlo1 = v in ? ? 1.29v 1.29v r uvlo2 ? ? ? ? ? ? + 11.6 a where v in + and v in C are the v in voltages when rising or falling respectively. for example, to disable the lt3580 for v in voltages below 3.5v using the single resistor configuration, choose: r uvlo1 = 3.5v ? 1.29v 1.29v ? ? ? ? ? ? + 11.6 a = 190.5k figure 7. configurable uvlo to activate the lt3580 for v in voltage greater than 4.5v using the double resistor configuration, choose r uvlo2 = 10k and: r uvlo1 = 4.5v ? 1.32v 1.32v 10k ? ? ? ? ? ? + 11.6 a = 22.1k internal undervoltage lockout the lt3580 monitors the v in supply voltage in case v in drops below a minimum operating level (typically about 2.3v). when v in is detected low, the power switch is deactivated, and while sufficient v in voltage persists, the soft-start capacitor is discharged. after v in is detected high, the power switch will be reactivated and the soft-start capacitor will begin charging. thermal considerations for the lt3580 to deliver its full output power, it is imperative that a good thermal path be provided to dissipate the heat generated within the package. this is accomplished by taking advantage of the thermal pad on the underside of the ic. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from the ic and into a copper plane with as much area as possible. thermal lockout if the die temperature reaches approximately 165c, the part will go into thermal lockout, the power switch will be turned off and the soft-start capacitor will be discharged. the part will be enabled again when the die temperature has dropped by ~5c (nominal). thermal calculations power dissipation in the lt3580 chip comes from four primary sources: switch i 2 r loss, npn base drive (ac), npn base drive (dc), and additional input current. the following formulas can be used to approximate the power losses. these formulas assume continuous mode operation, r uvlo2 (optional) 1.3v r uvlo1 3580 f07 v in v in active/ lockout gnd 11.6a at 1.3v C + shdn
lt3580 15 3580fg applications information so they should not be used for calculating efficiency in discontinuous mode or at light load currents. average input current: i in = v out ?i out v in ? switch i 2 r loss: p sw = (dc)(i in ) 2 (r sw ) base drive loss (ac): p bac = 13n(i in )(v out )(f) base drive loss (dc): p bdc = (v in )(i in )(dc) 50 input power loss: p inp = 7ma(v in ) where: r sw = switch resistance (typically 200m at 1.5a) dc = duty cycle (see the power switch duty cycle sec- tion for formulas) = power conversion efficiency (typically 88% at high currents) example: boost configuration, v in = 5v, v out = 12v, i out = 0.5a, f = 1.25mhz, v d = 0.5v: i in = 1.36a dc = 61.5% p sw = 228mw p bac = 270mw p bdc = 84mw p inp = 35mw total lt3580 power dissipation (p tot ) = 617mw thermal resistance for the lt3580 is influenced by the pres- ence of internal, topside or backside planes. to calculate die temperature, use the appropriate thermal resistance number and add in worst-case ambient temperature: t j = t a + ja ? p tot where t j = junction temperature, t a = ambient tempera- ture, ja = 43c/w for the 3mm 3mm dfn package and 35c/w to 40c/w for the msop exposed pad package. p tot is calculated above. v in ramp rate while initially powering a switching converter application, the v in ramp rate should be limited. high v in ramp rates can cause excessive inrush currents in the passive components of the converter. this can lead to current and/or voltage overstress and may damage the passive components or the chip. ramp rates less than 500mv/s, depending on component parameters, will generally prevent these issues. also, be careful to avoid hot-plugging. hot-plugging occurs when an active voltage supply is instantly connected or switched to the input of the converter. hot-plugging results in very fast input ramp rates and is not recommended. finally, for more information, refer to linear application note an88, which discusses voltage overstress that can occur when an inductive source impedance is hot-plugged to an input pin bypassed by ceramic capacitors. layout hints as with all high frequency switchers, when considering layout, care must be taken to achieve optimal electrical, thermal and noise performance. one will not get adver- tised performance with a careless layout. for maximum efficiency, switch rise and fall times are typically in the 5ns to 10ns range. to prevent noise, both radiated and conducted, the high speed switching current path, shown in figure 8, must be kept as short as possible. this is imple- mented in the suggested layout of a boost configuration in figure 9. shortening this path will also reduce the parasitic trace inductance. at switch-off, this parasitic inductance produces a flyback spike across the lt3580 switch. when operating at higher currents and output voltages, with poor layout, this spike can generate voltages across the lt3580 that may exceed its absolute maximum rating. a ground plane should also be used under the switcher circuitry to prevent interplane coupling and overall noise. the vc and fb components should be kept as far away as practical from the switch node. the ground for these components should be separated from the switch cur- rent path. failure to do so can result in poor stability or subharmonic oscillation.
lt3580 16 3580fg applications information c2, for best load regulation. you can tie the local ground into the system ground plane at the c3 ground terminal. the cut ground copper at d1s cathode is essential to obtain low noise. this important layout issue arises due to the chopped nature of the currents flowing in q1 and d1. if they are both tied directly to the ground plane before being combined, switching noise will be introduced into the ground plane. it is almost impossible to get rid of this noise, once present in the ground plane. the solution is to tie d1s cathode to the ground pin of the lt3580 before the combined currents are dumped in the ground plane as drawn in figure 2, figure 12 and figure 13. this single layout technique can virtually eliminate high frequency spike noise, so often present on switching regulator outputs. figure 8. high speed chopped switching path for boost topology board layout also has a significant effect on thermal re- sistance. the exposed package ground pad is the copper plate that runs under the lt3580 die. this is a good thermal path for heat out of the package. soldering the pad onto the board reduces die temperature and increases the power capability of the lt3580. provide as much copper area as possible around this pad. adding multiple feedthroughs around the pad to the ground plane will also help. figures 9 and 10 show the recommended component placement for the boost and sepic configurations, respectively. layout hints for inverting topology figure 11 shows recommended component placement for the dual inductor inverting topology. input bypass capaci- tor, c1, should be placed close to the lt3580, as shown. the load should connect directly to the output capacitor, 3580 f08 v out l1 sw gnd lt3580 d1 c2 c1 v in high frequency switching path load
lt3580 17 3580fg figure 9. suggested component placement for boost topology (both dfn and msop packages. not to scale). pin 9 (exposed pad) must be soldered directly to the local ground plane for adequate thermal performance. multiple vias to additional ground planes will improve thermal performance figure 10. suggested component placement for sepic topology (both dfn and msop packages. not to scale). pin 9 (exposed pad) must be soldered directly to the local ground plane for adequate thermal performance. multiple vias to additional ground planes will improve thermal performance figure 11. suggested component placement for inverting topology (both dfn and msop packages. not to scale). note cut in ground copper at diodes cathode. pin 9 (exposed pad) must be soldered directly to local ground plane for adequate thermal performance. multiple vias to additional ground planes will improve thermal performance applications information 3580 f10 v out v in 5 6 7 8 9 4 3 2 1 sw l1 l2 d1 c3 c2 c1 shdn sync gnd vias to ground plane required to improve thermal performance 3580 f11 v out v in 5 6 7 8 9 4 3 2 1 sw c1 c2 d1 c3 l1 l2 shdn sync gnd vias to ground plane required to improve thermal performance 3580 f09 v out v in c2 l1 c1 d1 5 6 7 8 9 4 3 2 1 sw shdn sync gnd vias to ground plane required to improve thermal performance
lt3580 18 3580fg applications information figure 12. switch-on phase of an inverting converter. l1 and l2 have positive di/dt figure 13. switch-off phase of an inverting converter. l1 and l2 currents have negative di/dt figure 14. 1.2mhz, 5v to 12v boost converter + + l1 l2 c2 C(v in + ? v out ? ) sw swx d1 q1 3580 f12 c1 c3 r load Cv out v in v cesat + + l1 l2 c2 v in + | v out | + v d sw swx d1 q1 c1 c3 r load Cv out v in v d 3580 f13 c2 10f v out 12v 550ma l1 4.2h d1 130k v in 5v v in sw 3580 f14 lt3580 75k 10k shdn gnd fb vc sync ss rt 1nf 0.1f c1 2.2f c1: 2.2f, 25v, x5r, 1206 c2: 10f, 25v, x5r, 1206 d1: microsemi ups120 l1: sumida cdr6d23mn-4r2
lt3580 19 3580fg typical applications 750khz, 5v to 40v, 150ma boost converter wide input range sepic converter with 5v output switches at 2.5mhz transient response with 400ma to 500ma output load step c2 2.2f v out 40v 150ma l1 47h d1 464k v in 5v v in sw 3580 ta02 lt3580 121k 10k shdn gnd fb vc sync ss rt 4.7nf 0.1f 47pf c1 2.2f c1: 2.2f, 25v, x5r, 1206 c2: 2.2f, 50v, x5r, 1206 d1: microsemi ups140 l1: sumida cdrh105r-470 c2 10f v out 5v, 600ma (v in = 5v or higher) 500ma (v in = 4v) 400ma (v in = 3v) 300ma (v in = 2.6v) l1 4.7h c3 1f l2 4.7h d1 46.4k v in 2.6v to 12v operating 12v to 32v transient v in sw 3580 ta03a lt3580 35.7k 10k shdn gnd fb vc sync ss rt 1nf 22pf 0.1f c1 2.2f c1: 2.2f, 35v, x5r, 1206 c2: 10f, 10v, x5r, 1206 c3: 1f, 50v, x5r, 0805 d1: microsemi ups140 l1, l2: tdk vlcf4020t-4r7n1r2 v out 100mv/div ac coupled i l1 +i l2 0.5a/div 100s/div v in = 12v 3580 ta03b
lt3580 20 3580fg typical applications vfd (vacuum flourescent display) power supply switches at 2mhz to avoid am band danger high voltage! operation by high voltage trained personnel only d1 d5 d2 d3 d4 c5 1f c4 1f c3 1f l1 10h 383k v in 9v to 16v 3.3v v in sw v out2 95v 80ma v out1 64v 40ma 3580 ta04 lt3580 r1 10 r2 10 45.3k 10k shdn gnd fb vc sync ss rt c6 1f c7 1f 2.2nf 0.1f 47pf c2 4.7f c1 4.7f c1, c2: 4.7f, 25v, x5r, 1206 c3-c7: 1f, 50v, x5r, 0805 d1-d4: on semiconductor mbr0540 d5: microsemi ups140 l1: sumida cdr6d28mnnp-100 r1, r2: 0.5w
lt3580 21 3580fg typical applications high voltage positive power supply uses tiny 5.8mm 5.8mm 3mm transformer and switches at 200khz danger high voltage! operation by high voltage trained personnel only start-up waveforms switching waveforms c2 68nf for any v out between 50v to 350v, choose r fb according to for 5v input, keep maximum output power at 1.58w for 3.3v input, keep maximum output power at 0.88w *may require multiple series resistors to comply with maximum voltage ratings v out 350v 4.5ma (v in = 5v) 2.5ma (v in = 3.3v) t1 1:10.4 d1 r fb 4.22m* v in 3.3v to 5v v in sw 3580 ta05a lt3580 d2 464k 10k shdn gnd 7, 8 5, 6 1 4 fb vc sync ss rt 10nf 100pf 0.47f c1 2.2f c1: 2.2f, 25v, x5r, 1206 c2: tdk c3225x7r2j683m d1: vishay gsd2004s dual diode connected in series d2: on semiconductor mbr0540 t1: tdk ldt565630t-041 ? ? v out C 1.215 83.3a r fb = 4.7h i primary 1a/div v out 50v/div 2ms/div 5v input no load 3580 ta05b i primary 1a/div v out 2v/div ac coupled 2s/div 5v input 4.5ma load 3580 ta05c
lt3580 22 3580fg typical applications high voltage negative power supply uses tiny 5.8mm 5.8mm 3mm transformer and switches at 200khz danger high voltage! operation by high voltage trained personnel only c2 68nf for any v out between C50v to C350v, choose r fb according to for 5v input, keep maximum output power at 1.58w for 3.3v input, keep maximum output power at 0.88w *may require multiple series resistors to comply with maximum voltage ratings v out C350v 4.5ma (v in = 5v) 2.5ma (v in = 3.3v) t1 1:10.4 d1 r fb 4.22m* v in 3.3v to 5v v in sw 3580 ta06 lt3580 464k 10k shdn gnd 7, 8 5, 6 1 4 fb vc sync ss rt 10nf 100pf 0.47f c1 2.2f c1: 2.2f, 25v, x5r, 1206 c2: tdk c3225x7r2j683m d1: vishay gsd2004s dual diode connected in series d2: on semiconductor mbr0540 t1: tdk ldt565630t-041 ? ? v out 83.3a r fb = 4.7h d2
lt3580 23 3580fg typical applications 5v to 12v boost converter switches at 2.5mhz and uses a tiny 4mm 4mm 1.7mm inductor efficiency and power loss vs load current transient response with 400ma to 500ma to 400ma output load step start-up waveforms c2 4.7f v out 12v 500ma l1 3.3h d1 130k v in 5v v in sw 3580 ta07a lt3580 35.7k 10k shdn gnd fb vc sync ss rt 2.2nf 0.1f 47pf c1 4.7f c1, c2: 4.7f, 25v, x5r, 1206 d1: microsemi ups120 l1: coilcraft lps4018-332ml load current (ma) 0 50 efficiency (%) power loss (w) 55 65 70 75 400 95 3580 ta07b 60 200 100 500 300 600 80 85 90 0 200 400 600 1400 800 1000 1200 i l 0.5a/div v out 0.5v/div ac coupled 100s/div 3580 ta07c i l 1a/div v out 5v/div v shdn 1v/div 2ms/div 500ma load 3580 ta07d
lt3580 24 3580fg typical applications C5v output inverting converter switches at 2.5mhz and accepts inputs between 3.3v to 12v efficiency and power loss vs load current c2 10f v out C5v 800ma (v in = 12v) 620ma (v in = 5v) 450ma (v in = 3.3v) l1 4.7h c3 1f d1 60.4k v in 3.3v to 12v v in sw 3580 ta08a lt3580 35.7k 10k shdn gnd fb vc sync ss rt 2.2nf 100pf 0.1f c1 2.2f c1: 2.2f, 25v, x5r, 1206 c2: 10f, 25v, x5r, 1206 c3: 1f, 50v, x5r, 0805 d1: central semi cmmsh1-40 l1, l2: coilcraft lsp4018-472ml l2 4.7h load current (ma) 0 40 efficiency (%) power loss (w) 45 55 60 65 400 85 3580 ta08b 50 200 100 500 300 700 600 70 75 80 0 200 400 600 1200 800 1000 v in = 5v
lt3580 25 3580fg package description 3.00 p 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.40 p 0.10 bottom viewexposed pad 1.65 p 0.10 (2 sides) 0.75 p 0.05 r = 0.125 typ 2.38 p 0.10 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (dd8) dfn 0509 rev c 0.25 p 0.05 2.38 p 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 p 0.05 (2 sides) 2.10 p 0.05 0.50 bsc 0.70 p 0.05 3.5 p 0.05 package outline 0.25 p 0.05 0.50 bsc dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698 rev c)
lt3580 26 3580fg package description ms8e package 8-lead plastic msop , exposed die pad (reference ltc dwg # 05-08-1662 rev f) msop (ms8e) 0210 rev f 0.53 p 0.152 (.021 p .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does not include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 C 0.38 (.009 C .015) typ 0.86 (.034) ref 0.65 (.0256) bsc 0 o C 6 o typ detail a detail a gauge plane 12 3 4 4.90 p 0.152 (.193 p .006) 8 8 1 bottom view of exposed pad option 7 6 5 3.00 p 0.102 (.118 p .004) (note 3) 3.00 p 0.102 (.118 p .004) (note 4) 0.52 (.0205) ref 1.68 (.066) 1.88 (.074) 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 1.68 p 0.102 (.066 p .004) 1.88 p 0.102 (.074 p .004) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.42 p 0.038 (.0165 p .0015) typ 0.65 (.0256) bsc 0.1016 p 0.0508 (.004 p .002) detail b detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref
lt3580 27 3580fg information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number f 06/10 added gnd to the pin configuration section. revised note 2 in the electrical characteristics section. revised graph g08 in the typical performance characteristics section. revised the applications information section. revised table 3 in the applications information section. revised figure 13 in the applications information section. updated drawing ta01a in the typical applications section. updated related parts table. 2 3 4 10-11 12 18 24 28 g 09/10 added h- and mp-grade information to absolute maximum ratings, order information, electrical characteristics and pin functions sections. added text at end of general guidelines and revised equations under avoiding subharmonic oscillations in applications information section. 2, 3, 5 8, 9 (revision history begins at rev f)
lt3580 28 3580fg linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0910 rev g ? printed in usa related parts typical application part number description comments lt1310 2a (i sw ), 40v, 1.2mhz high efficiency step-up dc/dc converter v in : 2.3v to 16v, v out(max) = 40v, i q = 3ma, i sd < 1a, thinsot? package lt1613 550ma (i sw ), 1.4mhz high efficiency step-up dc/dc converter v in : 0.9v to 10v, v out(max) = 34v, i q = 3ma, i sd < 1a, thinsot package lt1618 1.5a (i sw ), 1.25mhz high efficiency step-up dc/dc converter v in : 1.6v to 18v, v out(max) = 35v, i q = 1.8ma, i sd < 1a, ms10 package lt1930/lt1930a 1a (i sw ), 1.2mhz/2.2mhz high efficiency step-up dc/dc converter v in : 2.6v to 16v, v out(max) = 34v, i q = 4.2ma/5.5ma, i sd < 1a, thinsot package lt1931/lt1931a 1a (i sw ), 1.2mhz/2.2mhz high efficiency inverting dc/dc converter v in : 2.6v to 16v, v out(max) = 34v, i q = 4.2ma/5.5ma, i sd < 1a, thinsot package lt1935 2a (i sw ), 40v, 1.2mhz high efficiency step-up dc/dc converter v in : 2.3v to 16v, v out(max) = 40v, i q = 3ma, i sd < 1a, thinsot package lt1944/lt1944-1 (dual) dual output 350ma (i sw ), constant off-time, high efficiency step-up dc/dc converter v in : 1.2v to 15v, v out(max) = 34v, i q = 20a, i sd < 1a, ms10 package lt1945 (dual) dual output pos/neg 350ma (i sw ), constant off-time, high efficiency step-up dc/dc converter v in : 1.2v to 15v, v out(max) = 34v, i q = 20a, i sd < 1a, ms10 package lt1946/lt1946a 1.5a (i sw ), 1.2mhz/2.7mhz high efficiency step-up dc/dc converter v in : 2.6v to 16v, v out(max) = 34v, i q = 3.2ma, i sd < 1a, ms8e package lt1961 1.5a (i sw ), 1.25mhz high efficiency step-up dc/dc converter v in : 3v to 25v, v out(max) = 35v, i q = 0.9ma, i sd < 6a, ms8e package lt3436 3a (i sw ), 800khz, 34v step-up dc/dc converter v in : 3v to 25v, v out(max) = 34v, i q = 0.9ma, i sd < 6a, tssop16e package lt3467 1.1a (i sw ), 1.3mhz high efficiency step-up dc/dc converter v in : 2.6v to 16v, v out(max) = 40v, i q = 1.2ma, i sd < 1a, thinsot, 2mm 3mm dfn packages lt3477 42v, 3a, 3.5mhz boost, buck-boost, buck led driver v in : 2.5v to 25v, v out(max) = 40v, analog/pwm, i sd < 1a, qfn, tssop20e packages lt3479 3a full-featured dc/dc converter with soft-start and inrush current protection v in : 2.5v to 24v, v out(max) = 40v, analog/pwm, i sd < 1a, dfn, tssop packages 2mhz inverting converter generates C12v from a 5v to 12v input efficiency and power loss vs load current c2 10f v out C12v 500ma (v in = 12v) 350ma (v in = 5v) l1 10h c3 1f d1 147k v in 5v to 12v v in sw 3580 ta09a lt3580 45.3k 10k shdn gnd fb vc sync ss rt 2.2nf 47pf 0.1f c1 2.2f c1: 2.2f, 25v, x5r, 1206 c2: 10f, 25v, x5r, 1206 c3: 1f, 50v, x5r, 0805 d1: central semi cmmsh1-40 l1: sumida cdrh6d28np-100nc l2: sumida cdrh3d28np-220nc l2 22h load current (ma) 0 efficiency (%) power loss (mw) 70 80 400 3580 ta09b 60 50 100 200 300 50 150 250 350 90 65 75 55 85 600 1000 200 0 1400 400 800 1200 v in = 5v

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